RCA 1802 Instruction Set

00	IDL	Idle wait for Int/DMA
0N	LDN	M(R(N)) => D; FOR N not 0
1N	INC N	R(N) + 1 => R(N)
2N	DEC N	R(N) - 1 => R(N)
30	BR XX	M(R(P)) => R(P).0
31	BQ XX	IF Q=1, M(R(P)) => R(P).0
32	BZ XX	IF D=0, M(R(P)) => R(P).0
33	BDF XX	IF DF=1, M(R(P)) => R(P).0
34	B1 XX	IF EF1=1, M(R(P)) => R(P).0
35	B2 XX	IF EF2=1, M(R(P)) => R(P).0
36	B3 XX	IF EF3=1, M(R(P)) => R(P).0
37	B4 XX	IF EF4=1, M(R(P)) => R(P).0
38	SKP	R(P) + 1 => R(P)
39	BNQ XX	IF Q=0, M(R(P)) => R(P).0
3A	BNZ XX	IF D NOT 0, M(R(P)) => R(P).0
3B	BNF XX	IF DF=0, M(R(P)) => R(P).0
3C	BN1 XX	IF EF1=0, M(R(P)) => R(P).0
3D	BN2 XX	IF EF2=0, M(R(P)) => R(P).0
3E	BN3 XX	IF EF3=0, M(R(P)) => R(P).0
3F	BN4 XX	IF EF4=0, M(R(P)) => R(P).0
4N	LDA N	M(R(N)) => D; R(N)++
5N	STR N	D => M(R(N))
60	IRX	R(X) += 1
61	OUT 1	M(R(X)) => Bus; R(X)++; Nout=1
62	OUT 2	M(R(X)) => Bus; R(X)++; Nout=2
63	OUT 3	M(R(X)) => Bus; R(X)++; Nout=3
64	OUT 4	M(R(X)) => Bus; R(X)++; Nout=4
65	OUT 5	M(R(X)) => Bus; R(X)++; Nout=5
66	OUT 6	M(R(X)) => Bus; R(X)++; Nout=6
67	OUT 7	M(R(X)) => Bus; R(X)++; Nout=7
68	ILL	Illegal Operation
69	INP 1	Bus => M(R(X)); BUS => D; Nout=1
6A	INP 2	Bus => M(R(X)); BUS => D; Nout=2
6B	INP 3	Bus => M(R(X)); BUS => D; Nout=3
6C	INP 4	Bus => M(R(X)); BUS => D; Nout=4
6D	INP 5	Bus => M(R(X)); BUS => D; Nout=5
6E	INP 6	Bus => M(R(X)); BUS => D; Nout=6
6F	INP 7	Bus => M(R(X)); BUS => D; Nout=7
70	RET	M(R(X)) => (X,P); R(X)++; 1 => IE
71	DIS	M(R(X)) => (X,P); R(X)++; 0 => IE
72	LDXA	M(R(X)) => D; R(X)++
73	STXD	D => M(R(X)); R(X) += -1
74	ADC	M(R(X)) + D + DF => DF, D
75	SDB	M(R(X)) - D - (NOT DF) => DF, D
76	SHRC	D >> 1; LSB(D) => DF; 0 => MSB(D)
77	SMB	D - M(R(X)) - (NOT DF) => DF, D
78	SAV	T => M(R(X))
79	MARK	(X,P)=>T; (X,P)=>M(R(2)); P=>X; R(2) += -1
7A	REQ	0 => Q
7B	SEQ	1 => Q
7C	ADCI XX	M(R(P)) + D + DF => DF,D
7D XX	SDBI	M(R(P)) - D - (NOT DF) => DF,D
7E	SHLC	D << 1; MSB(D) => DF; DF => LSB(D)
7F XX	SMBI	D - M(R(P)) - (NOT DF) => DF,D
8N	GLO	R(N).0 => D
9N	GHI	R(N).1 => D
AN	PLO	D => R(N).0
BN	PHI	D => R(N).1
C0	LBR XXXX	M(R(P)),M(R(P+1)) => R(P).1,R(P).0
C1	LBQ XXXX	IF Q=1, M(R(P)),M(R(P+1)) => R(P).1,R(P).0
C2	LBZ XXXX	IF D=0, M(R(P)),M(R(P+1)) => R(P).1,R(P).0
C3	LBDF XXXX	IF DF=1, M(R(P)),M(R(P+1)) => R(P).1,R(P).0
C4	NOP	CONTINUE
C5	LSNQ	IF Q=0, R(P) += 2
C6	LSNZ	IF D!=0, R(P) += 2
C7	LSNF	IF DF=0, R(P) += 2
C8	LSKP	R(P) += 2
C9	LBNQ XXXX	IF Q=0, M(R(P)),M(R(P+1)) => R(P).1,R(P).0
CA	LBNZ XXXX	IF D!=0, M(R(P)),M(R(P+1)) => R(P).1,R(P).0
CB	LBNF XXXX	IF DF=0, M(R(P)),M(R(P+1)) => R(P).1,R(P).0
CC	LSIE	IF IE=1, R(P) += 2
CD	LSQ	IF Q=1, R(P) += 2
CE	LSZ	IF D=0, R(P) += 2
CF	LSDF	IF DF=1, R(P) += 2
DN	SEP N	N => P
EN	SEX N	N => X
F0	LDX	M(R(X)) => D
F1	OR	M(R(X)) OR D => D
F2	AND	M(R(X)) AND D => D
F3	XOR	M(R(X)) XOR D => D
F4	ADD	M(R(X)) + D => DF,D
F5	SD	M(R(X)) - D => DF,D
F6	SHR	D >> 1; LSB(D) => DF; 0 => MSB(D)
F7	SM	D - M(R(X)) => DF,D
F8	LDI XX	M(R(P)) => D
F9	ORI XX	M(R(P)) OR D => D
FA	ANI XX	M(R(P)) AND D => D
FB	XRI XX	M(R(P)) XOR D => D
FC	ADI XX	M(R(P)) + D => DF,D
FD	SDI XX	M(R(P)) - D => DF,D
FE	SHL	D << 1; MSB(D) => DF; 0 => LSB(D)
FF	SMI XX	D - M(R(P)) => DF,D

Example Programs

Use: select, copy, and paste to run

Name	Source Code	Machine Code
Idle	IDL	00
NOP Idle	NOP IDL	C400
NOP Loop	NOP NOP NOP NOP NOP BR 00	C4C4C4C4C43000
Set Q	SEQ IDL	7B00
Blink Q	REQ SEQ BR 00	7A7B3000
Slow Blink Q	GHI R1 LSZ REQ SKP SEQ INC R1 BR 00	91CE7A387B113000
Faster Slow Blink Q	GLO R1 LSZ REQ SKP SEQ INC R1 BR 00	81CE7A387B113000
Blink Q by PC Swap	GHI R0 (90) PHI R1 (B1) LDI 09 (F8 09) PLO R1 (A1) SEQ (7B) SEP R1 (D1) BR 05 (30 05) REQ (7A) SEP R0 (D0) BR 09 (30 09)	90B1F809A17BD130057AD03009
Skip Tests	SEQ SKP REQ LSKP REQ REQ LDI 00 LSZ REQ REQ LDI 01 LSZ REQ REQ IDL	7B387AC87A7AF800CE7A7AF801CE7A7A00
16 Bit Register 5 Counter	LDI 00 (F8 00) PLO R5 (A5) PHI R5 (B5) INC R5 (15) BR 04 (30 04) IDL (00)	F800A5B515300400
8 Bit Counter STN/LDN	LDI 0D (F8 0F) PLO R4 (A4) LDI 00 (F8 00) PHI R4 (B4) PLO RD (AF) PHI RD (BF) INC RD (1F) GLO RD (8F) STR R4 (54) GHI R0 (94) LDN R4 (04) BR 08 (30 08) IDL (00)	F80FA4F800B4AFBF1F8F549404300800
Count to 5 with Output	BR 07 (30 07) $ 01 (01) $ 02 (01) $ 03 (01) $ 04 (01) $ 05 (01) GHI R0 (90) PHI R5 (B5) LDI 02 (F8 02) PLO R5 (A5) SEX R5 (E5) OUT 4 (64) OUT 4 (64) OUT 4 (64) OUT 4 (64) OUT 4 (64) IDL (00)	3007010203040590B5F802A5E5646464646400
Count Forever with Output	BR 0B (30 0B) $ 00 (00) OUT 4 (64) DEC R4 (24) INC RF (1F) GLO RF (8F) STR R4 (54) LDN R4 (04) BR 03 (30 03) LDI 02 (F8 02) PLO R4 (A4) LDI 00 (F8 00) PHI R4 (B4) PLO RF (AF) PHI RF (BF) SEX R4 (E4) BR 03 (30 03) IDL (00)	300B0064241F8F54043003F802A4F800B4AFBFE4300300
Count Forever with Output and Q LED	00: 30 0D 02: 00 03: 7B 04: 64 05: 24 06: 1F 07: 8F 08: 7A 09: 54 0A: 04 0B: 30 03 0D: F8 02 0F: A4 10: F8 00 12: B4 13: AF 14: BF 15: E4 16: 30 03 18: 00	300D007B64241F8F7A54043003F802A4F800B4AFBFE4300300
Echo Input to Output	SEX R1 GHI R0 PHI R1 LDI 0A PL0 R1 INP 4 OUT 4 BR 01 $ 00	E190B1F80AA16C64300100
Fibonacci sequence up to 255	00: F8 00 02: BA 03: BB 04: BC 05: F8 1A 07: AA 08: F8 1B 0A: AB 0B: F8 00 0D: AC 0E: EA 0F: F4 10: 5A 11: 64 12: 2A 13: EB 14: F4 15: 5B 16: 64 17: 2B 18: 30 0E 1A: 00 1B: 01	Plain Hex Format: F800BABBBCF81AAAF81BABF800ACEAF45A642AEBF45B642B300E0001 Intel Hex Format: :1C000000F800BABBBCF81AAAF81BABF800ACEAF45A642AEBF45B642B300E0001CF :00001C01E3
Draw Green Square	GPort EQU 6 START ORG $00 LDI 00 PHI $0F PHI $0E LDI DATA PLO $0F SEX $0F LDI EDATA-DATA PLO $0E SEND OUT GPort DEC $0E GLO $0E BNZ SEND IDL ; Graphics commands DATA BYTE $03 ; Color BYTE $00 BYTE $FF BYTE $00 BYTE $01 ; Move BYTE $50 BYTE $50 BYTE $02 ; Draw BYTE $B0 BYTE $50 BYTE $02 ; Draw BYTE $B0 BYTE $B0 BYTE $02 ; Draw BYTE $50 BYTE $B0 BYTE $02 ; Draw BYTE $50 BYTE $50 BYTE $03 ; Color BYTE $00 BYTE $00 BYTE $00 EDATA END	:20000000F800BFBEF811AFEFF817AE662E8E3A0B000300FF0001505002B05002B0B0025047 :08002000B00250500300000083 :00002801D7
Draw Colored Square	GPort EQU 6 START ORG $00 LDI 00 ; Load 0 PHI $0F ; Zero F.1 PHI $0E ; Zero E.1 LDI DATA ; Commands PLO $0F ; F = Cmds SEX $0F ; X is F LDI EDATA-DATA ; Cmd Size PLO $0E ; E counts down SEND OUT GPort ; Output Cmd DEC $0E ; Count Down GLO $0E ; Check Count BNZ SEND ; Send if more IDL ; Done!! ; Graphics commands to send DATA BYTE $01 ; Move to ... BYTE $50 ; x: 50x BYTE $50 ; y: 50x BYTE $03 ; Set Red BYTE $FF ; Red: FF BYTE $00 ; Green: 00 BYTE $00 ; Blue: 00 BYTE $02 ; Draw to ... BYTE $B0 ; x: B0x BYTE $50 ; y: 50x BYTE $03 ; Set Green BYTE $00 ; Red: 00 BYTE $FF ; Green: FF BYTE $00 ; Blue: 00 BYTE $02 ; Draw to ... BYTE $B0 ; x: B0x BYTE $B0 ; y: B0x BYTE $03 ; Set Blue BYTE $00 ; Red: 00 BYTE $00 ; Green: 00 BYTE $FF ; Blue: FF BYTE $02 ; Draw to ... BYTE $50 ; x: 50x BYTE $B0 ; y: B0x BYTE $03 ; Set Yellow BYTE $FF ; Red: FF BYTE $FF ; Green: FF BYTE $00 ; Blue: 00 BYTE $02 ; Draw to ... BYTE $50 ; x: 50x BYTE $50 ; y: B0x EDATA ; End of Data END	:20000000F800BFBEF811AFEFF81FAE662E8E3A0B0001505003FF000002B0500300FF0002EF :10002000B0B0030000FF0250B003FFFF00025050C9 :00003001CF
Draw Square Spiral	; Draw a square spiral GPort EQU $6 RDel EQU $D RCmd EQU $C Step EQU $8 START ORG 00H LDI 0 PHI RDel PHI RCmd PLO RCmd LDI Delta PLO RDel SEX RCmd ; Clear to dark green LDI Cmd PLO RCmd LDI $4 STR RCmd OUT GPort LDI $00 STR RCmd OUT GPort LDI $60 STR RCmd OUT GPort LDI $00 STR RCmd OUT GPort ; Set color to green LDI Cmd PLO RCmd LDI $3 STR RCmd OUT GPort LDI $00 STR RCmd OUT GPort LDI $FF STR RCmd OUT GPort LDI $00 STR RCmd OUT GPort ; Move to the Center LDI Cmd PLO RCmd LDI $1 STR RCmd OUT GPort LDI $80 STR RCmd OUT GPort LDI $80 STR RCmd OUT GPort Draw ; Draw a line Up LDI Cmd PLO RCmd LDI $2 STR RCmd OUT GPort OUT GPort LDN RCmd SEX RDel SM SEX RCmd STR RCmd OUT GPort ; Draw a line Right LDI Cmd PLO RCmd LDI $2 STR RCmd OUT GPort LDN RCmd SEX RDel ADD SEX RCmd STR RCmd OUT GPort OUT GPort ; Increase step size SEX RDel LDI Step ADD BDF Done STR RDel SEX RCmd ; Draw a line Down LDI Cmd PLO RCmd LDI $2 STR RCmd OUT GPort OUT GPort LDN RCmd SEX RDel ADD SEX RCmd STR RCmd OUT GPort ; Draw a line Left LDI Cmd PLO RCmd LDI $2 STR RCmd OUT GPort LDN RCmd SEX RDel SM SEX RCmd STR RCmd OUT GPort OUT GPort ; Increase step size SEX RDel LDI Step ADD BDF Done STR RDel SEX RCmd BR Draw Done IDL Delta Byte Step Cmd Byte 0 Data Byte 1,2,3 END	:20000000F800BDBCACF889ADECF88AACF8045C66F8005C66F8605C66F8005C66F88AACF809 :20002000035C66F8005C66F8FF5C66F8005C66F88AACF8015C66F8805C66F8805C66F88AEF :20004000ACF8025C66660CEDF7EC5C66F88AACF8025C660CEDF4EC5C6666EDF808F43388AD :200060005DECF88AACF8025C66660CEDF4EC5C66F88AACF8025C660CEDF7EC5C6666EDF879 :0E00800008F433885DEC303E000800010203F6 :00008E0171
Bouncing Lines	Too large to show code	:20000000F800B8B9BABBBCBDBEBFF896ACF88CADF882AEF8A2A8F8C3A7F880ABF881AFEB9F :20002000F8045B662BF8005B662B662B662B7BEBD7EBF8015B662BF878AA0A5B662BF87944 :20004000AA0A5B662BF8025B662BF87AAA0A5B662BF87BAA0A5B662B7AF878AAF87CA9D86C :20006000F879AAF87DA9D8F87AAAF87EA9D8F87BAAF87FA9D8302E0032FA0A00FBFA0608B0 :2000800000000000000000000000000000336699CCFFFFFFFFFFFFFFFFFFFFFFCC9966336F :2000A000EED0097E33B40AE9F45A3BB2F75AF800F75930A10AE9F45A33C0F75AF800F759AF :2000C00030A1D0F803EF5F662FEC8CFFA03AD2F882AC66ED8DFFA03ADCF882AD66EE8EFFBB :0900E000A03AE6F882AE6630C2D7 :0000E90116
Draw Enterprise	Too large to show code	:20000000F800BFBEF814AFEFF800BEF8BEAE662E8E3A0E0003FFFFFF03FF80170600501638 :2000200040047BDEDBDE000000004A50DA5200000000425EABD0000000004A428A52000021 :2000400000007BDE8A5E00000000000000000000000000000000000007E000000000FFFF7A :20006000FFFF0006000100000001007FE001000000027FC03FE0FCFFFFFE400F00100480DF :2000800000007FC03FE004800000003FD04004800000000F082004807A1E0000079004803D :2000A00042100000187FFCF0721C0000300000104210000073FC00107BD0000030003FF022 :1200C00000000000180FC0000000000007F00000000050 :0000D2012D
CHIP-8	Too large to show code	:1800000091BBFF01B2B6F8CFA2F881B1F846A190B4F81BA4F801B5F821 :18001800FCA5D496B7E294BC45AFF6F6F6F63244F950AC8FFA0FF9F024 :18003000A605F6F6F6F6F9F0A74CB38CFC0FAC0CA3D3301B8FFA0FB34B :18004800453040226912D400000101010101010101010101010001016C :18006000007C75838B95B4B7BC91EBA4D970990506FA07BE06FA3FF6CC :18007800F6F6225207FA1FFEFEFEF1AC9BBC45FA0FADA7F8D0A693AFB0 :180090008732F3274ABD9EAE8E32A49DF6BD8F76AF2E30989D56168F3C :1800A8005616308E00ECF8D0A693A78D32D906F22D32BEF801A746F3FC :1800C0005C02FB0732D21C06F232CEF801A706F35C2C168CFC08AC3B02 :1800D800B3F8FFA6875612D49BBFF8FFAF935F8F32DF2F30E50042B530 :1800F00042A5D48DA78732AC2A2730F500000000000000000045A398AE :1801080056D4F881BCF895AC22DC1256D406B8D406A8D4640A01E68A1A :18012000F4AA3B289AFC01BAD4F881BA06FA0FAA0AAAD4E606BF93BE31 :18013800F81BAE2A1AF8005A0EF53B4B560AFC015A30404EF63B3C9F4E :18015000562A2AD400228652F8F0A7075A87F3171A3A5B12D42286520F :18016800F8F0A70A5787F3171A3A6B12D41585227395522545A586FAB4 :180180000FB5D445E6F33A821515D445E6F33A88D44507308C450730BF :1801980084E6622645A33688D43E88D4F8F0A7E745F4A586FA0F3BB279 :1801B000FC01B5D44556D445E6F456D445FA0F3AC40756D4AF22F8D3E0 :1801C800738FF9F052E607D256F8FFA6F8007E56D41989AE93BE99EE68 :1801E000F45676E6F4B95645F256D445AA86FA0FBAD4000000000000F1 :0801F8000000000000E0004BD4 :00000001FF
Test Address Lines	; Test all address lines ; Set Q and double address ; Reset Q, double address 0000: ; Code at 0000 7b ; SEQ c0 0004 ; LBR 0004 0004: ; Code at 0004 7a ; REQ c0 0008 ; LBR 0008 0008: ; Code at 0008 7b ; SEQ c0 0010 ; LBR 0010 0010: ; Code at 0010 7a ; REQ c0 0020 ; LBR 0020 0020: ; Code at 0020 7b ; SEQ c0 0040 ; LBR 0040 0040: ; Code at 0040 7a ; REQ c0 0080 ; LBR 0080 0080: ; Code at 0080 7b ; SEQ c0 0100 ; LBR 0100 0100: ; Code at 0100 7a ; REQ c0 0200 ; LBR 0200 0200: ; Code at 0200 7b ; SEQ c0 0400 ; LBR 0400 0400: ; Code at 0400 7a ; REQ c0 0800 ; LBR 0800 0800: ; Code at 0800 7b ; SEQ c0 1000 ; LBR 1000 1000: ; Code at 1000 7a ; REQ c0 2000 ; LBR 2000 2000: ; Code at 2000 7b ; SEQ c0 4000 ; LBR 4000 4000: ; Code at 4000 7a ; REQ c0 8000 ; LBR 8000 8000: ; Code at 8000 7b ; SEQ c0 fffc ; LBR fffc fffc: ; Code at fffc 7a ; REQ c0 0000 ; LBR 0000
Register Gymnastics (self-modifying code)	Too large to show code	90B1A1B2A2B3E2F840B4F804A4F850B5F805A5F860B6F806A6F870B7F807 A7F880B8F808A8F890B9F809A9F8A0BAF80AAAF8B0BBF80BABF8C0BCF80C ACF8D0BDF80DADF8E0BEF80EAEF8F0BFF80FAF94A384B483A4FBF03277F8 4FA2F801F452F851A2F801F452F852A2F801F452F854A2F801F452304F00

Test 0: LDN and IDL	GHI R0 (90) PHI R5 (B5) LDI 07 (F8 07) PLO R5 (A5) LDN R5 (05) IDL (00) A07 (3B)	90B5F807A505003B
Test 1 and 2: INC and DEC	LDI 00 (F8 00) PLO RF (AF) PHI RF (BF) INC RF (1F) INC RF (1F) INC RF (1F) DEC RF (2F) DEC RF (2F) DEC RF (2F) BR 04 (30 04)	f800afbf1f1f1f2f2f2f3004
Test 4: LDA	GHI R0 (90) PHI R5 (B5) LDI 0A (F8 0B) PLO R5 (A5) LDA RF (45) LDA RF (45) LDA RF (45) LDA RF (45) LDA RF (45) IDL (00) A0A (F0E1D2C3B4)	90B5F80BA5454545454500F0E1D2C3B4
Test 5: STR	GHI R0 (90) PHI R5 (B5) LDI 16 (F8 16) PLO R5 (A5) LDI BE (F8 BE) STR R5 (55) INC R5 (15) LDI BE (F8 EF) STR R5 (55) INC R5 (15) LDI BE (F8 BA) STR R5 (55) INC R5 (15) LDI BE (F8 BE) STR R5 (55) INC R5 (15) IDL (00) A16 (00000000)	90B5F816A5F8BE5515F8EF5515F8BA5515F8BE55150000000000
Test 6: IRX, OUT, INP	GHI R0 (90) PLO R5 (A5) PHI R5 (B5) SEX R5 (E5) IRX (60) IRX (60) OUT 4 (64) OUT 4 (64) OUT 4 (64) OUT 4 (64) LDI 16 (F8 16) PLO R5 (A5) INP 4 (6C) INC R5 (15) INP 4 (6C) INC R5 (15) INP 4 (6C) INC R5 (15) INP 4 (6C) INC R5 (15) IDL (00) IDL (00) IDL (00) IDL (00) IDL (00) IDL (00)	90A5B5E5606064646464F816A56C156C156C156C15000000000000
Test 7: Misc. ALU	IDL (00)	00
Test 8: GLO RN	LDI 77 (F8 77) PLO R5 (A5) LDI 00 (F8 00) GLO R5 (85) IDL (00)	F877A5F8008500
Test 9: GHI RN	LDI 77 (F8 77) PHI R5 (B5) LDI 00 (F8 00) GHI R5 (95) IDL (00)	F877B5F8009500
Test A: PLO RN	LDI 77 (F8 77) PLO R5 (A5) IDL (00)	F877A500
Test B: PHI RN	LDI 77 (F8 77) PHI R5 (B5) IDL (00)	F877B500
Test C: Long Branches	IDL (00)	00
Test D: SEP	GHI R0 (90) PHI R1 (B1) LDI 09 (F8 09) PLO R1 (A1) SEQ (7B) SEP R1 (D1) BR 05 (30 05) REQ (7A) SEP R0 (D0) BR 09 (30 09)	90B1F809A17BD130057AD03009
Test E: SEX	IDL (00)	00
Test F: Misc. ALU	IDL (00)	00

RCA 1802 JavaScript Simulation

Documentation and Examples

Introduction

Program File Format

Machine State Log

Machine State Reference

RCA 1802 Instruction Set

Example Programs

RCA 1802 JavaScript Simulation

Documentation and Examples -- Select -- Introduction Instruction Set Examples Logs Load

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RCA 1802 Instruction Set

Example Programs

Documentation and Examples

Machine State Log

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